1. Field of the Invention
The invention claimed herein generally pertains to a method for reducing the time needed to generate test cases, which are provided to test processors such as microprocessors. More particularly, the invention pertains to a method of the above type wherein respective test cases, after being generated, are executed and re-executed a number of times in connection with different processor threads, in order to produce a substantial amount of test data.
2. Description of the Related Art
When a system is designed that includes a microprocessor or the like, it is important to verify and validate the system design, in order to ensure that the processor operates as intended. Accordingly, processor testing tools are used to apply stressful tests to the processor. Results of the tests are monitored, and then compared with expected or intended results produced by either the first pass of a two-pass consistency test or simulation. Typically, the testing tools include specially prepared test patterns or test cases, wherein a test case comprises a collection or set of specified processor instructions, arranged for execution in a specified order.
In microprocessor testing, test cases can be provided by a baremetal kernel, which directs or manipulates the test cases based on user specified inputs at compile time. The kernel is usually composed of the following four basic tasks or routines: initialization; test case generation; test case execution; and test results verification. Initialization is done one time, while the test case generation, execution and results verification tasks are continually looped around through the processor. This will continue until the user stops the run, or a fault or failure is detected.
In test procedures of the type described above, generating or building the test cases is typically the task that is most time consuming. As complexity of the kernel generation code increases, the portion of the time of the under-test processor cycle that is devoted to the generation routine likewise increases. Moreover, if the collection or set of instructions that make up the test case is comparatively small, so that test case execution time is short, the test case generation time will frequently outweigh the test case execution time. This gap between test case generation and execution times widens, as the processor being tested is run through an increasing number of loops.
It would thus be beneficial to provide a method and system for processor testing, wherein the time required for test case generation is significantly reduced, relative to test case execution time. This would improve the over-all efficiency of the design verification procedure.